This invention generally relates to methods for protecting copper filled semiconductor features and more particularly to a method for producing a protective layer in metal filled semiconductor features.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities with increased device speed.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi layer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections.
FIG. 1, for example, shows a typical dual damascene structure having a metal filled feature 12, for example a via, overlying a conductive area 14, for example a trench line interconnect. In forming a damascene structure, via openings and trench line openings are etched into one or more insulating layers, e.g., 16 (referred to as IMD or ILD layers) and are back-filled with metal, for example copper. The IMD layers are preferably a low-k (low dielectric constant) insulating material which reduces signal delay times caused by parasitic capacitances. The process by which via openings (holes) and trench lines are selectively etched into the insulating layers is typically a photolithographic masking process, followed by a reactive ion etch (RIE) process, both of which are commonly known in the art.
Prior to filling the via opening with metal, a barrier layer 18, for example, tantalum nitride is deposited to cover the sidewalls and bottom of the feature such as a via opening to prevent, for example, copper diffusion into the low-k IMD layer 16 and to improve the adhesion of the copper filled feature. Although several different types of metal may be used, for example, copper, tungsten, and aluminum, copper metal, or alloys thereof are increasingly the metal of choice due to low resistivity. Typically a relatively pure (undoped) copper material is deposited to fill the via opening to form copper filled via 12. Copper may be deposited in several ways including physical vapor deposition methods or electroplating deposition methods. Electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes depositing a metal seed layer, preferably copper, over the barrier layer, and then electroplating a metal, again preferably copper, over the seed layer to fill the etched feature to form, for example, vias and trench lines. A seed layer is required to carry electrical current for electroplating, the seed layer preferably being continuous to provide for uniform deposition. The deposited layers and the dielectric layers are then planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature, for example, via 12.
Since copper is easily oxidized when exposed to moisture or oxygen containing ambient, typically a cap (protective layer) layer, e.g., 20 of silicon carbide (SiC) or silicon nitride (SiN) which additionally functions as an etching stop layer is formed over the metal filled feature e.g., via 12 and the IMD layer 16. The etching stop layer 20 is formed following a CMP process to planarize the IMD surface 16 and to remove excess metal remaining from the electroplating process. Following deposition of the etching stop layer, another IMD layer, e.g., 22 may be deposited to repeat the feature formation process to form a multi-layer semiconductor device.
Problems with the prior art damascene manufacturing process include the fact that the etching stop (protective cap) layer undesirably adds to the overall capacitance of the multilayer semiconductor device thereby contributing to signal delay times. Another problem is that the etching stop layer contributes to reduced adhesion strength between the multiple layers potentially resulting in interlayer dielectric peeling when subjected to stresses such as those induced by CMP polishing. Further, the etching stop layer, for example, a metal nitride, is believed to contribute to photoresist poisoning effects where nitrogen containing species absorbed into the IMD layer interfere with subsequent photoresist development processes.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for forming multiple layer devices where the advantages of a protective cap layer may be realized without the concomitant shortcomings of reduced interlayer adhesion strength, increased capacitance, and photoresist poisoning effects.
It is therefore an object of the invention to provide a method for forming multiple layer devices where the advantages of a protective cap layer may be realized without the concomitant shortcomings reduced interlayer adhesion strength, increased capacitance, and photoresist poisoning effects.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of forming a protective layer included in a metal filled semiconductor feature.
In a first embodiment according to the present invention, the method includes providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.
In related embodiments, the at least a portion includes a seed layer. Further, the seed layer is deposited according to a physical vapor deposition process. Further yet, the at least a portion includes an undoped metal portion electroplated over the seed layer.
In another embodiment, the method further includes the step of planarizing the substrate following step of conformally depositing to include partially removing the at least one metal layer to form an exposed surface. Further, the step of thermally treating is at least partially carried out in an oxidizing atmosphere to form a protective layer of dopant impurity containing oxidized material at the exposed surface. Further yet, the protective layer is formed at a thickness of between about 50 Angstroms and 500 Angstroms. Yet further, the method further includes the step of forming a dielectric insulating layer over the substrate to contact the protective layer.
In related embodiments the dopant impurities include at least one of titanium, zirconium, magnesium, and carbon. Further, the dopant impurities are present in an amount ranging between about 0.1 and about 10 weight percent. Further yet, the dopant impurities are present in an amount ranging between about 0.5 and about 5 weight percent.
In other related embodiments, the at least a portion includes an electroplated layer. Further, the at least one metal layer includes at least one of copper, tungsten, and aluminum.
In yet another embodiment, the at least one metal layer is deposited over a barrier layer. Further, the barrier layer is includes a metal nitride. Further yet, the metal nitride includes tantalum nitride.
In yet another embodiment, the at least one metal layer is deposited over the insulating dielectric material included in the substrate. Further, the method further includes the step of forming a dielectric insulating layer over the substrate following a planarization step and an oxidizing thermal treatment step to form a protective layer of oxidized dopant impurities at an exposed surface of the at least one metal layer.
In yet other related embodiments, the step of thermally treating is carried out over a temperature range of between about 250xc2x0 C. and about 450xc2x0 C. Further, the step of thermally treating is carried out for a period of time such that the measured resistivity of the at least one metal layer is within a range of about 25% of the value of undoped metal.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.